module shift_16( In, Cnt, Op, Out);
	input [15:0] In;
	input [3:0] Cnt;
	input [1:0] Op;
	output [15:0] Out;

//level 1 (shift/rotate 1 bit)
	wire [15:0] lev1;
	wire [15:0] out1;
	mux2_1 inst[13:0](.InA(In[13:0]), .InB(In[15:2]), .Out(lev1[14:1]), .S(Op[1]));
	mux4_1 inst1(.Out(lev1[0]), .InA(In[15]), .InB(1'd0), .InC(In[1]), .InD(In[1]),.S(Op));
	mux4_1 inst2(.Out(lev1[15]),.InA(In[14]), .InB(In[14]),.InC(In[0]), .InD(In[15]), .S(Op));
	mux2_1 inst3[15:0](.InA(In), .InB(lev1), .S(Cnt[0]), .Out(out1));

//leve 2 (shift/rotate 2 bits)
	wire [15:0] lev2;
	wire [15:0] out2;
	mux2_1 inst4[11:0](.InA(out1[11:0]), .InB(out1[15:4]), .Out(lev2[13:2]), .S(Op[1]));
	mux4_1 inst5[1:0](.Out(lev2[1:0]), .InA(out1[15:14]), .InB(2'b00), .InC(out1[3:2]), .InD(out1[3:2]), .S(Op));
	mux4_1 inst6[1:0](.Out(lev2[15:14]), .InA(out1[13:12]), .InB(out1[13:12]), .InC(out1[1:0]), .InD(In[15]), .S(Op));
	mux2_1 inst7[15:0](.InA(out1), .InB(lev2), .S(Cnt[1]), .Out(out2));

//level 3 (shift/rotate 4 bits)
	wire [15:0] lev3;
	wire [15:0] out3;
	mux2_1 inst8[7:0](.InA(out2[7:0]), .InB(out2[15:8]), .Out(lev3[11:4]), .S(Op[1]));
	mux4_1 inst9[3:0](.Out(lev3[3:0]), .InA(out2[15:12]), .InB(4'b0000), .InC(out2[7:4]), .InD(out2[7:4]), .S(Op));
	mux4_1 inst10[3:0](.Out(lev3[15:12]), .InA(out2[11:8]), .InB(out2[11:8]), .InC(out2[3:0]), .InD(In[15]), .S(Op));
	mux2_1 inst11[15:0](.InA(out2), .InB(lev3), .S(Cnt[2]), .Out(out3));

//level 4 (shift/rotate 8 bits)
	wire [15:0] lev4;
	mux4_1 inst12[7:0](.Out(lev4[7:0]), .InA(out3[15:8]), .InB(8'b00000000), .InC(out3[15:8]), .InD(out3[15:8]), .S(Op));
	mux4_1 inst13[7:0](.Out(lev4[15:8]), .InA(out3[7:0]), .InB(out3[7:0]), .InC(out3[7:0]), .InD(In[15]), .S(Op));
	mux2_1 inst14[15:0](.InA(out3), .InB(lev4), .S(Cnt[3]), .Out(Out));

endmodule

